1. Field of the Invention
The invention relates generally to the testing of logic circuits and, more particularly, to enhancing test coverage in an alternating-current (AC) scan design in a level-sensitive scan design (LSSD) and/or a logic built-in self test (LBIST).
2. Description of the Related Art
As integrated circuits (ICs) have become more densely packed with electronic components and more complex, the need for testing such circuits has grown significantly. Production testing of ICs was performed originally by manually creating test patterns that exercised the functional behavior of the ICs. IC designs were a combination of combinatorial random logic and simple sequential logic elements such as D-type flip flops and/or latches. The effectiveness of test patterns could be calculated by simulating them against a set of fault models.
One fault model is a “stuck-at” fault model. A stuck-at fault model assumes that a defect can be represented as a stuck terminal on a gate. Although the stuck-at fault model is only a failure model, there is some degree of correlation between defect coverage and stuck-at fault model coverage. A “stuck” terminal stays at its stuck value regardless of the values propagating to it. Therefore, to fully represent all possible stuck-at faults, we assume there is a possible stuck-at-0 and stuck-at-1 on each gate terminal. As design sizes grew, however, it became impossible to manually create functional patterns that would detect possible faults on all device pins. Even if it was practical to manually generate functional tests with adequate coverage, sequential logic within designs caused these functional pattern sizes to grow exponentially. Consequently, scan technology and structured approaches to design-for-test (DFT) were adopted.
Direct-current (DC) scan design provides access to internal sequential elements for test pattern control and observation. It reduces the sequential problem to a simpler combinational problem that lends itself to computational solutions. As a result, automated test pattern generation (ATPG) software tools can create very high coverage scan patterns even for the largest designs. DC scan is a form of scan where shifting and sampling occurs well below the device's normal operating frequency. This type of scan is effective for a pure structural approach (i.e. for stuck-at faults), but in general, timing performance cannot necessarily be verified with this type of scan.
Another type of scan is a form of scan test application called AC scan, where only the sample interval is required at the specified operating frequency in order to verify timing performance, as well as structural content. The scan data may be shifted at a different (typically slower) frequency. AC scan allows slower testers to be utilized and does not place unnecessary constraints on the design to be able to shift at-speed.
In order to provide a mechanism for testing complex circuitry, a number of built-in self test (BIST) methodologies have been employed including level-sensitive scan design (LSSD) techniques, which use master/slave latches having different clock phases to isolate each scan node. In the LSSD methodology, a long string of shift register latches (SRLs) is employed in a dual-function role that does not detract from normal circuit operation. In particular, the SRL string provides both normal input during circuit operation and also a mechanism for providing test input signals to the circuit for diagnostic purposes. These tests may be employed immediately subsequent to chip manufacture or may in fact be employed in the field to diagnose fault conditions. Depending on the source of input signals to the SRL string, either normal operations or test operations may be carried out.
In AC scan using LSSD techniques, test coverage may not be exhaustive when adjacent SRLs feed the same “cone of logic” within a combinatorial logic under test. Cone of logic is a well-known term in the field of the invention, and refers to a combinatorial logic having one output and one or more inputs influencing the output. Typically, a combinatorial logic may include a plurality of cones of logic. For example, if a combinatorial logic has three inputs and two outputs, the combinatorial logic has two cones of logic. When adjacent SRLs feed the same cone of logic, randomization of the input test patterns is lost, because the inputs to the same cone of logic may be dependent upon one another. Therefore, subsequent test patterns become highly correlated and the robustness of the tests decline.
U.S. Pat. No. 5,278,842 issued on Jan. 11, 1994, to Berry, Jr. et al. (“Berry”) is directed to this problem of adjacent SRLs feeding the same cone of logic in a logic circuit. Berry addresses this problem by wiring the scan path such that no two adjacent SRLs feed the same cone of logic either by inserting an SRL that does not feed a common cone of logic or by inserting a dummy SRL between any two SRLs and using every other SRL in the chain to feed the logic. That is to say, Berry proposes a special wiring technique for selectively associating the output signal lines of the logic circuit with the input signal lines of the logic circuit. In some cases, however, the special wiring technique presented in Berry may still require some dummy SRLs to be added to the SRL string. Adding dummy SRLs take up space in the logic circuit and complicate design consideration thereof.
Therefore, there is a need for a method and apparatus for enhancing test coverage.